This disclosure relates to a semiconductor device with inherent capacitances and to a method for its production. For this purpose, the semiconductor device has an inherent gate capacitance CG of CG=CGD+CGS (feedback capacitance plus gate-source capacitance) at the input between a control electrode and the power electrodes. In addition, the semiconductor device has an inherent drain capacitance CD of CD=CDS+CGD (drain-source capacitance plus feedback capacitance) at the output between the power electrodes.
These inherent capacitances are progressively reduced as the dimensions of power semiconductor devices become steadily smaller while reverse voltages and on-state currents remain unchanged. Furthermore, compensated semiconductor devices such as “CoolMOS” are characterised by a low area-specific on resistance and by significantly smaller dimensions than conventional MOSFETs of the same absolute on resistance. The smaller dimensions, in particular the smaller chip area, automatically result in lower inherent capacitances, so that a compensated semiconductor device switches considerably faster and more steeply than a conventional MOSFET.
In non-optimized applications, the very steep di/dt in particular can generate very high voltage peaks at unavoidable parasitic inductances in the switch-off process. In addition, a very steep du/dt can induce vibrations in the parasitic and inherent circuit components of the semiconductor device, which may affect its EMI behaviour.
In order to limit both du/dt and di/dt, a gate series resistor is often installed in such applications to slow the whole switching process. This however results in the loss of the fast switching advantage of a compensated device, and the reduction in switching losses is lost as well. It therefore appears to be expedient to avoid such series resistors and to find solutions which do not require such series resistors.
For these and other reasons, there is a need for the present invention.